Full-Time Senior Verification Engineer
Cambridge, UK | Full-time or Part-time | Permanent | Salary: £60,000 to £75,000 DOE
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
Riverlane’s mission is to make quantum computing useful, sooner. From climate change to healthcare, large and reliable quantum computers will help solve some of the world’s biggest challenges. Riverlane is building the quantum error correction layer to make this happen sooner. It’s a complex problem that requires a range of skills, talent and passion. We’re making remarkable progress and growing fast.
About the role
As a Senior Verification Engineer at Riverlane, you will start from scratch, defining IP, subsystem and system level tests to fully test our innovative solutions. This is a rare opportunity to shape and influence verification at Riverlane, having a far-reaching impact on our company-wide verification process and our products.
You will design and own the verification process for blocks that will form part of the world’s first control system for fault tolerant quantum computing. Using state of the art debugging techniques and tools, you will identify bugs in our products before they reach our end-users.
Our hardware is a scaled-out, real-time, low-latency system that synchronises high accuracy, high speed pulses. You will work closely with our hardware designers to maximise internal learnings and improve the quality of our processes and products to define, build and deliver effective verification solutions for this cutting-edge system.
At Riverlane, we are building something unique, complex and large-scale, so being comfortable with engineering to evolving specs is key. You are happy to get hands-on quickly in areas outside your own expertise, you work well with different people and have a ‘ship’ mentality. You will learn quantum computing along the way!
What you will do
As a trusted member of our Deltaflow Control team, you will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:
- Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
- Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
- Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.
You do not need a background in quantum computing! You will learn this along the way…
What we need
- Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
- A proactive and collaborative person who actively shares feedback and who can independently define the scope of work.
- Proven experience of testbench design with verification frameworks like UVM/OVM.
- Knowledge of SystemVerilog assertion (SVA).
- Exposure to different programming languages, such as C, C++ and Python
Even better if
- You have formal verification experience
What can you expect from us
- A comprehensive benefits package that includes private medical insurance, life insurance and a contributory pension scheme.
- Equity so that our team can share in the long-term success of Riverlane
- 28 days annual leave plus bank holidays and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities.
- A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget for each staff member.
How to Apply
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